Planar DMOS (double-diffused metal-oxide-semiconductor) technologies provide low-cost and simple integration of on-chip IC (integrated circuit) control circuitry. However, planar DMOS technologies tend to have a relatively high on resistance (Ron). Several approaches have been taken to reduce Ron of planar DMOS devices. For example, some planar DMOS technologies employ charge compensation implants which deplete out to form a charge compensation region which largely supports most of the electric field during the off-state and hence mostly determines the device breakdown voltage. Increasing breakdown voltage in this way allows for shorter channel lengths because the body region no longer supports most of the breakdown voltage, and greater doping in the drift/channel region of the device to reduce Ron. However, the resulting charge compensation structures cause threshold voltage (Vth) control and avalanche problems and do not reduce Ron as far as technically possible. Conventionally a polysilicon resist mask has been used to pattern deep and medium charge compensation implants. This process flow has several disadvantages.
For example, the subsequent surface body implant is also masked by the same polysilicon. The entire implant stack is then driven by a body diffusion (annealing) process. After processing, the body concentration in the channel region is determined by a combination of the body implant and poorly controlled charge compensation implant tails generated by non-vertical sidewalls. This results in a wide Vth distribution and poor Vth matching between multiple DMOS devices, for example between a DMOS device and a DMOS current sense cell. DMOS current sense cells are designed to generate a fraction of the normal DMOS current, but poor Vth control and hence poor matching makes current sense cells less accurate especially at low currents.
Also, large geometries are typically used in conventional DMOS technologies, resulting in a high Ron. To achieve charge balance, relatively wide charge compensation implants between the polysilicon gates must be balanced with correspondingly wide gate lengths. This combination also requires deep charge compensation implants, necessitating a thick poorly-controlled resist which also requires wide geometries.
Breakdown occurs under the charge compensation regions. The charge compensation regions are disposed under the entire body region, resulting in some avalanche current flowing under the source region. An intrinsic parasitic bipolar transistor is triggered when sufficient avalanche current flows laterally underneath the source, thereby restricting the maximum avalanche current.
Some conventional approaches use a so-called JFET (junction field-effect transistor) implant in the drift/drain region of a DMOS device to reduce Ron. However, the lack of charge compensation implants means that the JFET implant must be very shallow to avoid reducing the breakdown voltage of the device. The best Ron/breakdown voltage tradeoff is conventionally obtained by placing the peak pre-body JFET implant at or near the silicon surface and gradually reducing the concentration deeper into the silicon. This is typically achieved by implanting the JFET implant close to the silicon surface. However, applying the JFET implant near the silicon surface counter-dopes the body implant at the surface to some extent. This results in a Vth which is influenced by an additional implant, increasing the Vth distribution. This is particularly problematic when a DMOS current sense cell is included in the design. DMOS current sense cells are designed to generate a fraction of the normal DMOS current, but poor Vth control and hence matching makes current sense cells less accurate especially at low currents.
Furthermore, a JFET implant is not easily added to a conventional DMOS process flow with wide charge compensation regions because the higher doping produced by the JFET region necessitates narrower gate lengths to maintain the breakdown voltage. This is incompatible with the thick poorly-controlled resist required for the deep charge compensation implants described above.